1. Field of the Invention
The present invention relates to buffer circuits designed to be coupled to a common bus. In particular, it relates to protecting such buffers against bus-imposed output-node voltages lying outside the buffers' rail-to-rail voltage range. More particularly, this invention relates to "over-voltage" and "under-voltage" protection of buffers in their high-impedance state. It provides overvoltage protection for buffers having a high-potential-power-rail voltage lower than voltages which may be imposed on the common bus by the other output circuits coupled to that bus; it provides undervoltage protection for buffers having a low-potential-power-rail voltage higher than voltages which may be imposed on the common bus by the other circuits coupled to that bus.
2. Description of Prior Art
Developments in the field of digital electronic circuits over the past few years have increased the variety of circuits which may end up connected to a common bus. This has increased the likelihood that the output voltage imposed on the bus by one circuit may be deleterious to one or more of the other circuits connected to the bus. For example, buffer circuits are now being produced which are designed to be powered by high-potential power rails V.sub.cc having considerably lower voltages than has been the case previously; it is important to be able to integrate these new circuits with buffers powered by the higher V.sub.cc which--until recently--were customary. The big shift has been from MOSFET circuits with V.sub.cc levels at a nominal voltage of 5 volts to MOSFET circuits with V.sub.cc levels at a nominal voltage of 3.3 volts. (These circuits are occasionally referred to as "3-volt circuits" or "3-volt buffers." Future developments will include circuits utilizing even lower V.sub.cc values. Consequently, the comments made here regarding circuits incorporating high-potential power rails of nominal voltages of 3.3 and 5, respectively, and a low-potential power rail at GND, should be taken as applying to any situation where the voltage of either power rail varies among the buffers coupled to a common bus.) Circuits using the nominal 3.3-volt V.sub.cc comply with the new JEDEC Standard 8-1A, which should be compared with JEDEC Standards 18 and 20, for 5-volt digital circuits. Under 8-1A, V.sub.oL --logic-low--is in the range 0.36-0.55 volts and V.sub.oH --logic-high--is in the range 2.0-2.4 volts. This compares with the logic levels under Standards 18 and 20, where V.sub.oL =0.36-0.55 volts and V.sub.oH =3.65-4.4 volts.
One key observation regarding the different standards is that the entire range of logic-high under the 5-volt standards exceeds the V.sub.cc level under JEDEC Standard 8-1A. This means that when sub-circuits complying with these different Standards are combined into a single extended circuit, a number of subtle problems have to be solved in order to ensure that the 3.3-volt high-potential power rail does not serve as a sink for current originating at the 5-volt high-potential rail. The present invention addresses this problem in the context of an array of output buffers coupled to a common bus but powered by high-potential power rails at different voltages. For definiteness, the different buffers will be referred to as 3.3-volt and 5-volt buffers, respectively. Nevertheless the approach of the present invention is not limited to this combination. Indeed, the buffer of interest may need to be protected not just against MOSFET buffers with high output voltages; it may also need protection against buffers with bipolar outputs only slightly above the V.sub.cc of the buffer of interest. Furthermore, the same broad approach will serve to provide protection to an output buffer connected to a common bus capable of being driven negative with respect to the buffer's low-potential power rail.
When the output node of an unprotected 3.3-volt buffer is driven to a voltage corresponding to logic-high for a 5-volt buffer, a current path will be set up between the high-potential power rail of the 5-volt buffer and that of the 3.3-volt buffer--indeed between the 5-volt buffer and all of the unguarded 3.3-volt buffers coupled to the common bus. This will result at best in excessive power consumption and at worst in temporary or permanent malfunctioning of the circuit, as the high-potential power rail of the 3.3-volt buffer is "corrupted" by the higher potential. The reason for this is clear from the circuit layout and physics of the included devices. The typical output buffer has a PMOS output pullup transistor and an NMOS output pulldown transistor. In the simple circuit the PMOS transistor's drain is connected directly to the buffer's output node and its source is connected to the buffer's high-potential power rail V.sub.cc, as is this PMOS transistor's bulk (sometimes referred to as the "NWELL" or "backgate"). The overvoltage threat is of greatest concern for the buffer in its inactive, high-Z state, since typically it is only then that the other buffers will be current-sourcing to the common bus. A high-Z buffer's pullup and pulldown stages should both present a high impedance to the bus. With respect to the pullup stage, the inactive buffer's output-pullup-transistor-gate will be held at logic-high to ensure that the pullup transistor is "off," that is, that it has no source-to-drain conduction channel. Unfortunately, the unprotected pullup transistor presents an alternate conduction route to an overvoltage imposed at the output node, namely, its drain-to-bulk pn junction, as can be seen by the nature of the device and the circuit. This pn junction will be forward biased by an overvoltage at the buffer's output node. A typical (enhancement mode) PMOS transistor in an integrated-circuit chip will have two p.sup.+ regions, one for the drain and the other for the source, embedded in a large n-doped region, the "NWELL." Therefore, if the drain (connected to the output node) is made sufficiently positive with respect to the bulk (connected to V.sub.cc), this junction will become forward-biased and current pass through it from the buffer's output node (and hence the bus) to the high-potential rail powering the buffer.
Note that the PMOS pullup transistor described above is turned on by making its gate (connected elsewhere in the buffer) sufficiently negative with respect to either p.sup.+ region such that holes diffuse to the surface of the NWELL in sufficient quantity to set up a p-type channel linking drain and source, i.e., linking the two p.sup.+ regions. The minimum gate-to-source voltage necessary to establish a minimal channel is the PMOS transistor's threshold voltage, V.sub.TP. This threshold voltage can be made to vary over a wide range by the particular fabrication techniques used. (For depletion-mode PMOS transistors, there is a channel present even when the source-to-gate voltage is zero; for enhancement-mode devices, the transition voltage can be reduced to close to zero.)
There have been previous attempts to circumvent the problem caused by overvoltages imposed on a buffer's output node, attempts to make the buffer "overvoltage tolerant." The simples approach has started at the obvious place, the coupling between V.sub.cc and the output node at the pullup transistor's drain-bulk pn junction. The bulk-source connection has been broken, and the bulk coupled directly to a "pseudo power rail," PV.sub.cc, introduced into the circuit. Switching means also introduced to the circuit provide that PV.sub.cc is coupled either to the actual high-potential power rail V.sub.cc or to the output node. In effect, the switching means is a voltage-comparator which couples to the pullup transistor bulk whichever of its two inputs-that from the output node and that from its high-potential power rail V.sub.cc --is at the greater voltage. A particular related-art circuit using this approach is described in application Ser. No. 08/024,942 filed by the present inventor on Mar. 2, 1993: Overvoltage-Tolerant Output Buffer Circuit. The basic output buffer circuit in question is set out in FIG. 1. PMOS transistor QP4 is the output pullup transistor of the circuit, which is to be coupled to a bus at the output node OUT. Note that QP4's bulk, instead of being tied directly to the source node and hence to the high-potential power rail V.sub.cc, is coupled to line PV.sub.cc, the "pseudo-high-potential-power-rail." PV.sub.cc is connected to the output of the comparator COMP, the inputs for which are, respectively, V.sub.cc and the output node OUT.
In the buffer of FIG. 1, NMOS transistor QN6 is the output pulldown transistor, driven by pulldown-transistor driver transistor QN4. Transistor QN5 is the pulldown-transistor disabler. NMOS transistor QN1 is the pullup-transistor driver. QN2, with its gate tied to the enable complement input EB, is the pullup transistor disabler. Finally, low-V.sub.TN transistor serves in the active bi-state buffer to pull up the gate of output pulldown transistor QN6 whenever a logic-low signal is received at the data input IN.
The output-guarding aspects of the circuit in FIG. 1 can be understood as follows. As long as only logic-low and -high signals commensurate in amplitude to those produced by this buffer appear on the bus, the voltage at the output node OUT will always be lower than V.sub.cc, and the comparator will couple PV.sub.cc to the true high-potential power rail; PV.sub.cc will therefore be at voltage V.sub.cc. Under these circumstances the buffer acts just as it would without the overvoltage protection, like the circuit that has its pullup transistor bulk connected in common to its source. On the other hand, for output voltages greater than V.sub.cc the comparator ensures that PV.sub.cc is coupled directly to the output node. This means that the pullup transistor's bulk will be at the same potential as its drain and consequently that no current will pass through the drain-bulk junction. The alternate current path between the bus and V.sub.cc has thereby been closed off. Unfortunately, without more, this advantage can be at the expense of providing a direct path through the turned-on pullup transistor QP4. In the unprotected circuit, the pullup transistor's gate will be held at voltage V.sub.cc while the buffer is in its high-Z state, to ensure that it remains off. However, with the drain (and the bulk) of QP4 at the voltage of PV.sub.cc, the gate may become negative with respect to the drain/bulk by more than V.sub.TP ; this will turn on QP4 and provide a direct path from OUT to the high-power potential rail. To avoid this, a feedback transistor QP1 with its gate connected to the enable input E is coupled between PV.sub.cc and the gate of QP4. With the buffer disabled, QP1 is held on by the logic-low E voltage. This results in PV.sub.cc being applied to the gate of QP4 during this period; hence it eliminates the QP4 gate-to-bulk voltage and results in QP4 being held off. One final "fix" is used in FIG. 1 in order to completely contain an overvoltage at the output node; this is the use of the NMOS transistor QN1--rather than a PMOS transistor--as the driver for the pullup transistor QP4 (and for the insertion of the invertor I to ensure proper logic function) and for the use of a second NMOS transistor QN2 as the pullup disabler driver. Conventionally, PMOS transistors coupled between V.sub.cc and the pullup transistor gate are used for both of these functions. Were that done in this circuit, the overvoltage on the pullup transistor gate would bull its way through these driver transistors to the high-potential power rail. In short, the over-voltage would find its way back to V.sub.cc thorough the channels and/or the drain-isolation pn junctions of those PMOS driver transistors. The NMOS transistors used as the pullup transistor drivers in FIG. 1, in contrast, constitute blocking transistors for an overvoltage. As noted, to accommodate this substitution the data input signals must be complemented to maintain correct logic, all as shown in FIG. 1. To ensure that the NMOS transistors QN1 and QN2 can charge the gate of QP4 high enough to hold it off, NMOS transistors with low turn-on threshold voltages V.sub.TN (and hence low drop along the channel when they are on) are used--as low as 0.4-0.5 volts, in contrast with the typical 0.85 volts. In fact, with some circuit adjustments, these can be chosen to be depletion-mode transistors to ensure well-controlled low threshold values. The symbol with the double line joining drain to source is used to indicate that a special low-V.sub.TP transistor, possibly a depletion-mode transistor, is used at that location.
Unfortunately, there is no ideal comparator available such as is implied in the discussion of the circuit of FIG. 1. There is no comparator so sensitive that it will select the higher of two inputs, regardless of how small the voltage difference between them. In FIG. 2, the related art is shown with a real, as opposed to an ideal, comparator. As will be seen, this comparator, made up of the PMOS pair QP5 and QP6, will be unable to distinguish between input voltages that differ by less than V.sub.T.
The principal current path of QP6 lies between OUT and PV.sub.cc and QP6's gate is at fixed-potential V.sub.cc. (Note that the bulk of QP6 is tied to PV.sub.cc, as is the bulk of QP5.) The operation and limitations of the comparator circuit of FIG. 2 can be understood by considering the various signals that can be imposed on the buffer's output node OUT while the buffer is in its high-Z state (pullup transistor QP4 and pulldown transistor QN6 both held off).
First consider the common bus to be held at a logic-low voltage V.sub.oL (&gt;GND) by one of the other circuits attached to the bus. This will cause QP5 to be on; with its source at V.sub.cc and its gate at V.sub.oL its source-to-gate voltage is considerably greater than the threshold needed to turn it on. With QP5 on, the high-potential power rail V.sub.cc is coupled directly to the pseudo-rail PV.sub.cc : the potential on the pseudo-rail will be the same as on the high-potential power rail V.sub.cc. It follows that QP6, with no voltage drop between its bulk/source and its gate, will be cut off. Since, by definition, the voltage imposed at OUT is lower than V.sub.cc --the potential of QP4's bulk--the pn junction joining the drain and bulk of QP4 will be reverse-biased, preventing any current path between OUT and V.sub.cc.
Next consider that--with the buffer depicted in FIG. 1 still inactive--the bus is driven to a logic-high which is less than V.sub.cc by an amount .vertline.V.sub.TP .vertline. or greater. Nothing will change; QP5 will continue to be on and QP6 will continue to be off, for the same reasons as before, and PV.sub.cc consequently will remain at the potential V.sub.cc.
Next consider that one of the 5-volt buffers coupled to the bus outputs a logic-high signal V.sub.oH &gt;(V.sub.cc +V.sub.TP). The gate bias of QP5 will become positive with respect to its bulk/source and this transistor will be shut off. The pn junction of QP6 which couples the OUT node to the bulk (at V.sub.cc) will become forward-biased, effectively increasing the QP6 bulk voltage to a level which is positive with respect to its gate by more than V.sub.TP, thus turning QP6 on and coupling the output node OUT to the pseudo-rail PV.sub.cc.
With the pseudo-rail controlled in the way set out above, now consider that the bus voltage drops back again to a voltage lower than V.sub.cc by an amount greater than V.sub.TP, i.e., that the voltage at OUT becomes less than (V.sub.cc -.vertline.V.sub.TP .vertline.). This serves to immediately turn on QP5, reconnecting the high-potential rail V.sub.cc directly to PV.sub.cc and hence to the bulk of QP4 and to the source of QP6. Since the gate of QP6 always is fixed at V.sub.cc, this cuts off QP6.
In spite of the protection afforded by the protection circuit utilizing the comparator described above, it is clear that there is a "dead zone" in which the difference between the V.sub.cc and the output node voltage is insufficient for the comparator to act. In particular, consider the bus making a transition from a logic-low voltage to a voltage greater than V.sub.cc but by an amount less than the threshold voltage V.sub.TP for the PMOS transistors QP5 and QP6. With continuing reference to FIG. 1, it can be seen that QP6, initially cut off, will remain off and that QP5, initially on, will be cut off. The result is that PV.sub.cc will be left floating as far as the comparator is concerned; it will be connected to neither comparator input. Consider what happens when PV.sub.cc is riding at V.sub.oH+ when this occurs. This is a higher voltage than will be present on any of the other elements of the circuit. This means in particular that this high voltage will appear on the bulk and gate of the pullup transistor QP4, while the drain and source of QP4 will be much lower. This presents the hazard that leakage from the charged pseudo-power line PV.sub.cc through the thin gate oxide of QP4 to QP4's source or drain regions will set up a fault condition--i.e., that excess leakage through QP4 and onto the bus will occur, i.e., that the unit will fail the output leakage specification. There is another phenomenon to consider also and that is that once the overvoltage has leaked away from PV.sub.cc, PV.sub.cc will end up clamped at a voltage V.sub.cc -V.sub.f, due to its connection to the high-potential power line across the source-bulk junction of QP4. (Here, V.sub.f is the voltage drop across the forward-biased bulk-source pn junction of QP4.) The primary concern here is that when PV.sub.cc drops significantly below V.sub.cc the drain potential of QP1--which follows its source potential: PV.sub.cc --is no longer great enough to ensure that the channel of QP4 does not form. I.e., QP4 may turn on even though the buffer is supposed to be in its high-Z state. The gate of QP4 must never be allowed to become negative with respect to the source of QP4 by more than .vertline.V.sub.TP .vertline.. Since V.sub.f can exceed .vertline.V.sub.TP .vertline., the circuit of FIG. 2 may lead to a violation of this condition.
It should be noted that the possibility of the output node being driven above V.sub.cc, but not by very much, is not just a theoretical one. In general, the other buffers coupled to the common bus can include some with bipolar output stages, which will put out logic-high voltages directly in the range of present concern, namely (V.sub.cc +.vertline.V.sub.TP .vertline.)&gt;V.sub.oH &gt;V.sub.cc.
There are also circumstances where the output node can be driven to voltages below that of the low-potential power rail of the buffer. Without protection, the output pulldown transistor will provide a current leakage path. In the simple output buffer, the output node will be connected directly to the drain of the pulldown transistor. See, e.g., QN6 in FIG. 1. The drain will be an n.sup.+ region in a PWELL, which in turn will be connected directly to the low-potential power rail. If the control node connected to the drain is negative with respect to the low-potential power rail, typically GND, the pn junction between the bulk and drain of the output pulldown transistor will be forward biased and current will flow from the low-potential power rail out to the bus. By this means, the low-potential power rail will be corrupted by the bus voltage in a similar manner to that described above for overvoltages. By analogy, this can be characterized as an undervoltage problem.
What is needed therefore is a circuit which will permit the output node of an output buffer to be driven above V.sub.cc without allowing an increase in I.sub.oZ --the current drained from the bus into an inactive buffer through the buffer's output node--or I.sub.cc --the current passing directly between the two power rails of the buffer--even for those cases where the increment by which the output node voltage exceeds V.sub.cc is less than VT.sub.TP. What is also needed is a circuit which will permit the output node of an output buffer to be driven to voltages below the buffer's low-potential power rail without allowing an increase in I.sub.oZ or I.sub.cc, even for those cases where the increment by which the output node voltage goes below the low-potential power rail voltage is less than V.sub.TP. A final constraint is that these power-rail protection needs be met with the introduction of a minimum quantity of additional circuitry.